View CXD2931R_219311.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CXD2931R
1 chip GPS LSI
Description The CXD2931R is a dedicated LSI for the GPS (Global Positioning System) satellite-based position measurement system. This LSI contains a 32-bit RISC CPU, 2M-bit MASK ROM, RAM, UART, timer, and others. This LSI, used together with the RF LSI (CXA1951AQ), enables the configuration of a 2-chip system capable of measuring its position anywhere on the globe. Features * 16-channel GPS receiver capable of simultaneously receiving 16 satellites * Supports differential GPS -- Comforms to RTCM SC-104 Ver. 2.1 -- Supports DARC * All-in-view measurement * 2-satellite measurement * Timer supporting GPS time * High performance 32-bit RISC CPU * 256K-byte program ROM * 36K-byte RAM * 3-channel UART -- Baud rate generator -- Supports 1.2K, 2.4K, 4.8K, 9.6K, 19.2K and 38.4K baud -- Supports 1/2/4-byte buffer mode * 23-bit general-purpose I/O port capable of defining input/output independently for each bit Structure Silicon gate CMOS IC 144 pin LQFP (Plastic)
Absolute Maximum Ratings * Supply voltage VDD VSS - 0.5 to 4.6 V * Input voltage VI VSS - 0.5 to VDD + 0.5 V * Output voltage VO VSS - 0.5 to VDD + 0.5 V * Operating temperature Topr -40 to +85 C * Storage temperature Tstg -50 to +150 C Recommended Operating Conditions * Supply voltage VDD 3.0 to 3.6 * Operating temperature Topr Input/Output Pin Capacitance * Input capacitance CIN * Output capacitance COUT * I/O capacitance CI/O -40 to +85
V C
9 (Max.) 11 (Max.) 11 (Max.)
pF pF pF
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E99702-PS
CXD2931R
Performance * 16-channel GPS receiver * High performance 32-bit RISC CPU * Reception frequency 1575.42MHz (L1 band, CA code)
* Reception sensitivity (using the CXA1951AQ in the RF block) -130dBm or less * Time to first fix (time until initial measurement after power-on) Cold Start (without ephemeris and almanac) 35 to 60s Warm Start (without ephemeris with almanac) 33 to 50s Hot Start (with ephemeris and almanac) 6 to 20s Reacquisition Time (interrupt recovery time) Less than 5 minutes: < 3 to 6s 5 minutes or more: < 6 to 10s * Positioning accuracy Stand alone (GPS unit only) D-GPS (differential GPS) * Measurement data update time * Communication method * All-in-view measurement * 2-satellite measurement * High performance 32-bit RISC CPU The noted values may be exceeded depending on the operating environment and other conditions. 1: < 30m 3: < 90m 1: < 6m 3: < 18m Every 1s Sony standard serial communication Supports NMEA-0183
Antenna
CXA1951AQ RF Converter
0V
0V
TCXO
IF TXD
CXD2931R 16ch GPS Processor
RXD
GPS receiver system diagram using the CXD2931R -2-
CXD2931R
Block Diagram
DC0 to 5/PORT (16:21)
DADR (0:15)
PORT (0:15)
IADR (0:18)
IB (0:15)
DB (0:7)
ICS0, 1
XCS0
DWR
DRD
IWR
IRD
TEST0, 1 RUN BIU ICST0, 1 XROMW HOLD NMI PMI IODBK HOLDA SINT/PORT (22) 32bit RISC CLKO CLKOUT TCXOS CLKS CLKI
256K Byte ROM
EXRS PWRST
36K Byte SRAM VDD x 10 TXD0 to 2 RXD0 to 2 VSS x 10 UART (Baud Rate Generator) x 3
TIMER x 3 AVD 16ch GPS DSP 8bit ADC AVS VRT VRB
XTCXO
TCXO
ITCXO
OTCXO
CCKO
CCKI
IF0O
IF0
TOSEL
-3-
AVIN
CXD2931R
Pin Configuration
DADR15
DADR14
DADR13
DADR12
DADR10
DADR11
DADR9
DADR8
DADR7
DADR6
DADR5
DADR4
DADR3
DADR2
DADR1
DADR0
XCS0
DWR
DRD
IB15
IB14
IB13
IB12
IB10
IB11
DB5
DB4
DB3
DB2
DB1
DB0
VDD
VDD
VSS
VSS
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 DB6 109 DB7 110 SINT/PORT22 111 DCS0/PORT21 112 VDD 113 DCS1/PORT20 114 DCS2/PORT19 115 DCS3/PORT18 116 DCS4/PORT17 117 DCS5/PORT16 118 PORT15 119 PORT14 120 VSS 121 PORT13 122 PORT12 123 PORT11 124 PORT10 125 PORT9 126 PORT8 127 PORT7 128 VDD 129 PORT6 130 PORT5 131 PORT4 132 PORT3 133 PORT2 134 PORT1 135 PORT0 136 VSS 137 TXD2 138 RXD2 139 TXD1 140 RXD1 141 TXD0 142 RXD0 143 VDD 144 72 IB8 71 IB7 70 VSS 69 IB6 68 IB5 67 IB4 66 IB3 65 IB2 64 IB1 63 VDD 62 IB0 61 IADR18 60 IADR17 59 IADR16 58 IADR15 57 IADR14 56 IADR13 55 VSS 54 IADR12 53 IADR11 52 IADR10 51 IADR9 50 IADR8 49 IADR7 48 IADR6 47 VDD 46 IADR5 45 IADR4 44 IADR3 43 IADR2 42 IADR1 41 XROMW 40 ICS1 39 VSS 38 ICS0 37 IRD
1 AVD
2 AVIN
3 VRT
4 VRB
5 AVS
6 VSS
7 TCXO
8 XTCXO
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VDD CLKO CLKI CLKS CLKOUT OTCXO CCKI TEST0 TEST1 CCKO ICST0 ICST1 IF0O IF0 TCXOS VSS VDD VSS VDD RUN PWRST HOLD HOLDA IODBK EXRS IWR NMI PMI
-4-
IB9
CXD2931R
Pin Configuration Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Symbol AVD AVIN VRT VRB AVS VSS TCXO XTCXO VDD OTCXO TEST0 TEST1 CCKI CCKO VSS ICST0 ICST1 IF0 IF0O TCXOS VDD HOLD NMI PMI HOLDA IODBK EXRS PWRST VSS CLKI CLKO CLKS CLKOUT VDD RUN I/O -- I I I -- -- I O -- O I I I O -- I I I O I -- I I I O O I I -- I O I O -- O A/D converter power supply. Analog input. Reference input. A/D converter GND. GND TCXO binary conversion circuit/crystal oscillator. Power supply. TCXO clock output. Test. (Low level fixed) Description
Timer oscillation. (32.768kHz 100ppm) GND Test. (Low level fixed)
IF signal binary conversion circuit. TCXO select. (Low: TCXO/2, High: TCXO through) Power supply. Hold input signal. (High: Hold) Non maskable interrupt. Program maskable interrupt. Hold acknowledge signal. Break signal for debugging. Reset input signal. Connect to main power supply. Leave open during backup. GND CPU clock oscillation circuit. CPU clock select signal. (Low: TCXO, High: CLKI) CPU clock output. Power supply. Signal indicating CPU operating status. -5-
CXD2931R
Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
Symbol IWR IRD ICS0 VSS ICS1 XROMW IADR1 IADR2 IADR3 IADR4 IADR5 VDD IADR6 IADR7 IADR8 IADR9 IADR10 IADR11 IADR12 VSS IADR13 IADR14 IADR15 IADR16 IADR17 IADR18 IB0 VDD IB1 IB2 IB3 IB4 IB5 IB6 VSS
I/O O O O -- O I I/O I/O I/O I/O I/O -- I/O I/O I/O I/O I/O I/O I/O -- I/O I/O I/O I/O I/O I/O I/O -- I/O I/O I/O I/O I/O I/O -- GND -6- (MSB) GND Power supply.
Description Write signal for external expansion memory. Read signal for external expansion memory. Chip select 0 for external expansion memory. GND Chip select 1 for external expansion memory. Wait signal for external expansion memory. (High: Wait) (LSB)
Address signal for external expansion memory.
Address signal for external expansion memory.
Address signal for external expansion memory.
(LSB) Data bus I/O for external expansion memory. Power supply.
Data bus I/O for external expansion memory.
CXD2931R
Pin No. 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
Symbol IB7 IB8 IB9 IB10 VDD IB11 IB12 IB13 IB14 IB15 DRD DWR XCS0 DADR0 DADR1 VSS DADR2 DADR3 DADR4 DADR5 DADR6 DADR7 DADR8 DADR9 VDD DADR10 DADR11 DADR12 DADR13 DADR14 DADR15 DB0 DB1 VSS
I/O I/O I/O I/O I/O -- I/O I/O I/O I/O I/O O O O I/O I/O -- I/O I/O I/O I/O I/O I/O I/O I/O -- I/O I/O I/O I/O I/O I/O I/O I/O -- (MSB) (LSB) Power supply. (MSB) Power supply.
Description
Data bus I/O for external expansion memory.
Data bus I/O for external expansion memory.
Read signal for external expansion data memory. Write signal for external expansion data memory. Chip select signal for external expansion data memory. (LSB) Address signal for external expansion data memory. GND
Address signal for external expansion data memory.
Address signal for external expansion data memory.
Data bus I/O for external expansion data memory. GND
-7-
CXD2931R
Pin No. 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138
Symbol DB2 DB3 DB4 DB5 DB6 DB7 SINT/PORT22 DCS0/PORT21 VDD DCS1/PORT20 DCS2/PORT19 DCS3/PORT18 DCS4/PORT17 DCS5/PORT16 PORT15 PORT14 VSS PORT13 PORT12 PORT11 PORT10 PORT9 PORT8 PORT7 VDD PORT6 PORT5 PORT4 PORT3 PORT2 PORT1 PORT0 VSS TXD2
I/O I/O I/O I/O I/O I/O I/O I/O I/O -- I/O I/O I/O I/O I/O I/O I/O -- I/O I/O I/O I/O I/O I/O I/O -- I/O I/O I/O I/O I/O I/O I/O -- O GND General-purpose I/O port. Power supply. General-purpose I/O port. GND General-purpose I/O port. (MSB)
Description
Data bus I/O for external expansion data memory.
External interrupt input signal/general-purpose I/O port. This pin can be used as a general-purpose I/O port according to the internal registers. Chip select for external expansion data memory/general-purpose I/O port. This pin can be used as a general-purpose I/O port according to the internal registers. Power supply.
Chip select for external expansion data memory/general-purpose I/O port. These pins can be used as a general-purpose I/O port according to the internal registers.
UART transmission data output (channel 2) -8-
CXD2931R
Pin No. 139 140 141 142 143 144
Symbol RXD2 TXD1 RXD1 TXD0 RXD0 VDD
I/O I O I O I --
Description UART reception data input (channel 2) UART transmission data output (channel 1) UART reception data input (channel 1) UART transmission data output (channel 0) UART reception data input (channel 0) Power supply.
-9-
CXD2931R
Electrical Characteristics DC Characteristics Item Input voltage (1) (CMOS level) Input voltage (2) (5V interface) Output voltage (1) Symbol High level VIH (1) Low level VIL (1) 0.7 x VDD Condition Min. 0.7 x VDD (VDD = 3.0 to 3.6V, Topr = -40 to +85C) Typ. Max. VDD 0.2 x VDD 5.5 0.2 x VDD VDD - 0.4 0.4 VDD - 0.4 0.4 Unit V V V V V V V V V 0.4 20 4 55 70 50 V A mA -- -- 5 4 3 2 Applicable pins 1
High level VIH (2) Low level VIL (2)
High level VOH (1) IOH = -4.0mA Low level VOL (1) IOL = 4.0mA
Output voltage (2)
High level VOH (2) IOH = -8.0mA Low level VOL (2) IOL = 8.0mA
Output voltage (3)
High level VOH (3) IOH = -12.0mA VDD - 0.4 Low level VOL (3) ISTB IDD IOL = 12.0mA VDD = 3.0V VDD = 1.8V f = 18.414MHz
Current consumption in standby mode Supply current
Applicable pins 1 Pins 11, 12, 16, 17, 20, 22 to 24, 32, 41 2 Pins 62, 64 to 69, 72 to 74, 76 to 80, 84, 85, 87 to 94, 96 to 103, 105 to 112, 114 to 120, 122, 128, 130 to 136, 139, 141, 143 3 Pins 10, 25, 26, 33, 35, 42 to 46, 48 to 54, 56 to 61, 81 to 83, 138, 140, 142 4 Pins 38, 40, 62, 64 to 69, 71 to 74, 76 to 80, 84, 85, 87 to 94, 96 to 103, 105 to 112, 114 to 120, 122 to 128, 130 to 136 5 Pins 36, 37
- 10 -
CXD2931R
AC Characteristics (1) When inputting a pulse to the TCXO pin (VDD = 3.0 to 3.6V, Topr = -40 to +85C)
1/fTCK tTH TCXO tTL
When inputting a binary-converted signal Item TCXO clock frequency TCXO clock pulse width Symbol fTCK Min. Typ. - 3ppm 10 Typ. 18.414 Max. Typ. + 3ppm Unit MHz ns
tTH, tTL
0.01F 0.8Vp-p VDD/2 1M 8 7
When performing binary conversion with the TCXO and XTCXO pins (Pins 7 and 8)
(2) When performing self-oscillation with the CCKI and CCKO pins (VDD = 3.0 to 3.6V, Topr = -40 to +85C)
220pF 13 220pF 10M 14 32.768kHz 100ppm
(3) IF signal input (VDD = 3.0 to 3.6V, Topr = -40 to +85C)
0.01F 0.8Vp-p VDD/2 1M 19 18
(4) When performing self-oscillation with the MCKI, MCKO pins (VDD = 3.0 to 3.6V, Topr = -40 to +85C)
15pF 30 15pF X'tal 1M 31
- 11 -
CXD2931R
Battery Backup Mode The battery backup mode is activated when the power for the GPS receiver is turned off and power-on reset goes to low level. The timer clock continues to operate even when power-on reset goes low, but all other clock are fixed high and the LSI is set to the low power consumption mode. At this time, the RAM data is held and the registers are initialized. Battery backup mode is canceled by setting power-on reset to high.
10 clocks Power-on reset EXRS
PWRST 100ms or more Timer clocks CCKI, CCKO
Other clocks TCXO, XTCXO, CLKI, CLKO
Normal outputs TXD0 to 2, OTCXO, HOLDA
Fixed low
Tri-state outputs IODBK, RUN, CLKOUT Tri-state outputs ICS0, ICS1, IADR[18:1], IRD, IWR, DRD, DWR, XCS0
Fixed low
Hi-Z
Bidirectional (Input) SINT, IB[15:0], DCS0 to 5, DADR[15:0], DB[7:0], PORT[15:0] (Outut)
Fixed low Hi-Z
Inputs RXD0 to 2, ITCXO, IF0 to 2, HOLD, NMI, PMI
Fixed low
- 12 -
CXD2931R
CXD2931R Initialization CXD2931R initialization is started by setting the reset input signal EXRS (Pin 27) to low level. The timing should satisfy the conditions noted below. 1. During power-on (power-on reset) (VDD = 3.0 to 3.6V, Topr = -40 to +85C)
VDD Power supply, PWRST (Pin 28) 100ms or more VDD/2 EXRS (Pin 27)
VDD [V]
GND
The PWRST (Pin 28) signal should rise simultaneously with the power supply. The EXRS (Pin 27) signal should rise 100ms or more after the power supply and the PWRST signal have risen. Note that the PWRST signal should be left open during battery backup. 2. Initialization during operation (VDD = 3.0 to 3.6V, Topr = -40 to +85C)
Power supply, PWRST (Pin 28) VDD EXRS (Pin 27) 100s or more VDD/2
VDD [V]
GND
The internal registers can be initialized during operation by setting the EXRS (Pin 27) signal to low level for 100s or more. Keep the PWRST (Pin 28) signal at high level at this time.
- 13 -
CXD2931R
* External Command Fetch Timing (XROMW = 0)
CLKOUT (a) (b) IADR (c) ICS0, ICS1 (e) IRD (g) IB (16) (h) (f) (d)
No. (a) (b) (c) (d) (e) (f) (g) (h)
Item Read cycle time (Fex: @20MHz) Address delay time Chip select fall delay time Chip select rise delay time Read signal fall delay time Read signal rise delay time Read data setup time Read data hold time
Min. -- -- 2 2 1 1 23 0
Typ. 100 -- -- -- -- -- -- --
Max. -- 5 10 9 3 5 -- --
Unit ns ns ns ns ns ns ns ns
The load capacitance = 30pF.
* External Command Fetch Timing (XROMW = 1)
CLKOUT
IADR
ICS0, ICS1
IRD IB (16)
- 14 -
CXD2931R
* External Data Access Timing (ICS0, ICS1/XROMW = 0) (1) Read (half-word access/XROMW = 0)
CLKOUT (a) (b) IADR (c) ICS0, ICS1 (e) IRD (g) IB (16) (h) (f) (d)
(2) Write (half-word access/XROMW = 0)
CLKOUT (a) (b) IADR (c) ICS0, ICS1 (i) IWR (k) IB (16) (l) (j) (d)
No. (a) (b) (c) (d) (e) (f) (g) (h) (i) (j) (k) (l)
Item Read/write cycle time (Fex: @20MHz) Address delay time Chip select fall delay time Chip select rise delay time Read signal fall delay time Read signal rise delay time Read data setup time Read data hold time Write signal fall delay time Write signal rise delay time Write data established time Write data hold time - 15 -
Min. -- -- 2 2 1 1 23 0 0 0 -- 5
Typ. 100 -- -- -- -- -- -- -- -- -- -- --
Max. -- 5 10 9 3 5 -- -- 1 2 5 --
Unit ns ns ns ns ns ns ns ns ns ns ns ns
The load capacitance = 30pF.
CXD2931R
(3) Read (word access/XROMW = 0)
CLKOUT
IADR
ICS0, ICS1
IRD IB H (16) L (16)
(4) Write (word access/XROMW = 0)
CLKOUT
IADR
ICS0, ICS1
IWR IB L (16) H (16)
- 16 -
CXD2931R
* External Data Access Timing (ICS0, ICS1/XROMW = 1) (1) Read (half-word access/XROMW = 1)
CLKOUT
IADR
ICS0, ICS1
IRD IB (16)
(2) Write (half-word access/XROMW = 1)
CLKOUT
IADR
ICS0, ICS1
IWR IB (16)
(3) Read (word access/XROMW = 1)
CLKOUT
IADR
ICS0, ICS1
IRD IB H (16) L (16)
(4) Write (word access/XROMW = 1)
CLKOUT
IADR
ICS0, ICS1
IWR IB L (16) H (16)
- 17 -
CXD2931R
* External Data Access Timing (XCS0, DCS0 to 5/no data wait) (1) Read (byte access/no data wait)
CLKOUT (a) (b) DADR (c) XCS0, DCS0 to 5 (e) DRD (g) DB (8) (h) (f) (d)
(2) Write (byte access/no data wait)
CLKOUT (a) (b) DADR (c) XCS0, DCS0 to 5 (i) DWR (k) DB (8) (l) (j) (d)
No. (a) (b) (c) (d) (e) (f) (g) (h) (i) (j) (k) (l)
Item Read/write cycle time (Fex: @20MHz) Address delay time Chip select fall delay time Chip select rise delay time Read signal fall delay time Read signal rise delay time Read data setup time Read data hold time Write signal fall delay time Write signal rise delay time Write data established time Write data hold time - 18 -
Min. -- -- 4 4 2 3 16 0 0 0 -- 5
Typ. 100 -- -- -- -- -- -- -- -- -- -- --
Max. -- 9 13 13 8 10 -- -- 1 2 7 --
Unit ns ns ns ns ns ns ns ns ns ns ns ns
The load capacitance = 30pF.
CXD2931R
(3) Read (half-word access/no data wait)
CLKOUT
DADR
XCS0, DCS0 to 5
DRD DB H (8) H (8)
(4) Write (half-word access/no data wait)
CLKOUT
DADR
XCS0, DCS0 to 5
DWR DB L (8) H (8)
(5) Read (word access/no data wait)
CLKOUT
DADR
XCS0, DCS0 to 5
DRD DB HH (8) HL (8) LH (8) LL (8)
(6) Write (word access/no data wait)
CLKOUT
DADR
XCS0, DCS0 to 5
DWR DB LL (8) LH (8) HL (8) HH (8)
- 19 -
CXD2931R
* External Data Access Timing (XCS0, DCS0 to 5/data wait = 1) (1) Read (byte access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to 5
DRD DB (8)
(2) Write (byte access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to 5
DWR DB (8)
(3) Read (half-word access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to 5
DRD DB H (8) L (8)
(4) Write (half-word access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to 5
DWR DB L (8) H (8)
- 20 -
CXD2931R
(5) Read (word access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to 5
DRD DB HH (8) HL (8) LH (8) LL (8)
(6) Write (word access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to 5
DWR DB LL (8) LH (8) HL (8) HH (8)
* External Data Access Timing (XCS0, DCS0 to 5/data wait = 2) (1) Read (byte access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to 5
DRD DB (8)
(2) Write (byte access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to 5
DWR DB (8)
- 21 -
CXD2931R
(3) Read (half-word access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to 5
DRD DB H (8) L (8)
(4) Write (half-word access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to 5
DWR DB L (8) H (8)
(5) Read (word access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to 5
DRD DB HH (16) HL (16) LH (16) LL (16)
(6) Write (word access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to 5
DWR DB LL (16) LH (16) HL (16) HH (16)
- 22 -
CXD2931R
Package Outline
Unit: mm
144PIN LQFP (PLASTIC)
22.0 0.2 20.0 0.1 108 109 73 1.7 MAX 1.4 0.1
72
B
A 144 37
1
0.5
36 b 0.08 M S S
0.1
S
0.1 0.05
b = 0.22 0.05
(21.0)
0 to 10 DETAIL A
0.5 0.15
DETAIL B : SOLDER
0.145 0.04
(0.125)
DETAIL B : PALLADIUM
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-144P-L01 LQFP144-P-2020 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 1.3 g
- 23 -
0.125 0.04
(0.2)
b = 0.20 0.03

▲Up To Search▲

Price & Availability of CXD2931R

	To Download CXD2931R Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .